The subject invention generally concerns the field of trigger buses in test and measurement instruments and specifically concerns WIRE-OR bus expansion between two test and measurement instrument chassis.
Modem test and measurement instruments have the capability of monitoring a plurality of channels simultaneously. For example, when a TLA 720 Logic Analyzer, manufactured by Tektronix, Inc., Beaverton, Oreg., is equipped to capacity with five 136-channel modules, it is capable of monitoring up to 680 channels. Signals at each of these input terminals may be acquired in response to a trigger signal asserted on a Trigger Bus. Acquisition of the data may be required when any of a variety of trigger sources detects a particular triggering condition. For example, a user may desire the instrument to trigger on detection of a glitch, upon detection a runt signal (a signal of lesser than normal, improper, amplitude), or upon detection of a signal that failed to complete within a specified time period. A detector for each of these (and many other) conditions will produce its own trigger signal. A Trigger Bus is a commonly-used method for combining multiple trigger signals for use by an acquisition system.
A WIRE-OR Trigger Bus generally employs a plurality of open-collector transistor bus drivers, each having its collector connected to a common bus conductor that is coupled to a source of positive potential via a pull-up resistor. When no driver is active, the bus is pulled to a high logic level potential by the pull-up resistor. When any of the drivers is actively conducting (i.e., sinking current through the pull-up resistor), the bus is pulled to a low logic level state. The term WIRE-OR is used to describe this arrangement because it produces an output that corresponds to that of a traditional logic-OR function. That is, if one or more of the input signals assume an active state, then the output is driven to an active state. noted at this point that what is being described is a Trigger Bus and not a Data Bus. Data buses are concerned with data integrity, and commonly employ tri-state drivers and anti-collision software or circuitry to ensure that data from only one driver is applied to the data bus at any given time.
In contrast, for a trigger bus, any actual trigger signal may be combined with any number of other trigger signals, without concern. Note that it is important that all receivers coupled to a Trigger Bus receive all of the trigger signals. By WIRE-ORing the trigger signals, each receiver will respond to the first of the triggers that pulls the Trigger Bus to its active state. The above-described WIRE-OR Bus is well-known in VXI applications, and is defined by VXI Bus Specification VXI-11, Rev. 1.0, Jul. 17, 1995.
It is important to note that, when using such WIRE-OR Buses, one must ensure that the propagation delay time of the bus is much less than the rise time of the signals to be applied to the bus. Unfortunately, this consideration generally limits WIRE-OR buses to a practical physical length of about two feet (roughly 61 cm.). An undesirable phenomenon known as xe2x80x9ccurrent-sharingxe2x80x9d also tends to limit the practical physical length of the WIRE-OR bus because xe2x80x9cglitchesxe2x80x9d (i.e., spurious switching signals) begin to appear on a Trigger Bus as the physical length of the bus is increased beyond the two-foot (61 cm.) limit.
The limited practical physical length of the Trigger Bus raises an interesting problem for an engineer who needs to expand the WIRE-OR Bus to accommodate more trigger sources or receivers, yet must also conform to the requirements of the WIRE-OR Bus structure defined by the above-identified VXI Bus Specification. What is needed is an arrangement that would conform to the WIRE-OR Bus structure specification and also permit expansion to a further WIRE-OR Bus structure physically located at a distance substantially greater than the two-foot (61cm) limit noted above.
An expanded WIRE-OR Bus structure has a first WIRE-OR Bus arrangement and a second WIRE-OR Bus arrangement. Each of the first and second WIRE-OR Bus arrangements have connected thereto at least one driver element and at least one receiver element. An intelligent bi-directional signal coupling circuit includes a buffer element, a bus arbiter, and a bus driver amplifier. The coupling circuit couples signals between the first WIRE-OR bus and the second WIRE-OR bus, and prevents signals originating on one of the WIRE-OR buses from being coupled back to the same (i.e., originating) WIRE-OR bus.